Digital India RISC-V (DIR-V) program
Recently Union Minister of State for Electronics and IT Shri Rajeev Chandrasekhar has addressed the Digital India RISC-V (DIR-V) seminar organized by IIT Madras in Chennai through virtual medium.
The event was organized by the Ministry of Electronics and Information Technology, IIT Madras and IIT-Madras Innovative Technologies Foundation.
In his address, he emphasized on the government’s vision for DIR-V and said that it currently aims to create a strong ecosystem for RISC-V through effective public-private partnership and collaboration with higher educational institutions like IIT Madras.
About RISC-V:
- RISC stands for ‘Reduced Instruction Set Computer’ and ‘V’ stands for fifth generation.
- RISC-V Foundation was established in the year 2015 and IIT Madras was one of its founding members.
- RISC-V instruction set architecture (ISA) enables a new era of processor innovation through liberal standard interoperability. Its purpose is to provide new open-layer, extensible software and hardware for the framework that will support computer design and innovation for the next 50 years.
- Professor Kamakoti developed India’s first indigenously designed microprocessor ‘Shakti’ based on RISC-V ISA.
- The Government of India started the DIR-V (Digital India RISC-V) microprocessor program in the year 2022, with the basic objective of preparing microprocessors for the future worldwide by the month of December 2023.
Source – The Hindu
